-- $Id: $
-- File name:   tb_IN_BLOCK.vhd
-- Created:     4/11/2011
-- Author:      Brandon Davis
-- Lab Section: 337-06
-- Version:     1.0  Initial Test Bench

library ieee;
--library gold_lib;   --UNCOMMENT if you're using a GOLD model
use ieee.std_logic_1164.all;
--use gold_lib.all;   --UNCOMMENT if you're using a GOLD model

entity tb_IN_BLOCK is
generic (Period : Time := 40 ns);
end tb_IN_BLOCK;

architecture TEST of tb_IN_BLOCK is

  function INT_TO_STD_LOGIC( X: INTEGER; NumBits: INTEGER )
     return STD_LOGIC_VECTOR is
    variable RES : STD_LOGIC_VECTOR(NumBits-1 downto 0);
    variable tmp : INTEGER;
  begin
    tmp := X;
    for i in 0 to NumBits-1 loop
      if (tmp mod 2)=1 then
        res(i) := '1';
      else
        res(i) := '0';
      end if;
      tmp := tmp/2;
    end loop;
    return res;
  end;

  component IN_BLOCK
    PORT(
         BCLK : IN std_logic;
         EN : IN std_logic;
         RST : IN std_logic;
         SDI : IN std_logic;
         STRB : IN std_logic;
         SYNC : IN std_logic;
         DATA : OUT std_logic_vector (15 DOWNTO 0);
         DataReadyB : OUT std_logic;
         DataReadyW : OUT std_logic
    );
  end component;

-- Insert signals Declarations here
  signal BCLK : std_logic;
  signal EN : std_logic;
  signal RST : std_logic;
  signal SDI : std_logic;
  signal STRB : std_logic;
  signal SYNC : std_logic;
  signal DATA : std_logic_vector (15 DOWNTO 0);
  signal DataReadyB : std_logic;
  signal DataReadyW : std_logic;

-- signal <name> : <type>;

begin

CLKGEN: process
  variable BCLK_tmp: std_logic := '0';
begin
  BCLK_tmp := not BCLK_tmp;
  BCLK <= BCLK_tmp;
  wait for Period/2;
end process;

  DUT: IN_BLOCK port map(
                BCLK => BCLK,
                EN => EN,
                RST => RST,
                SDI => SDI,
                STRB => STRB,
                SYNC => SYNC,
                DATA => DATA,
                DataReadyB => DataReadyB,
                DataReadyW => DataReadyW
                );

--   GOLD: <GOLD_NAME> port map(<put mappings here>);

process
  variable F40 : std_logic_vector(39 downto 0);
  variable Dat384 : std_logic_vector(383 downto 0);
  begin

    RST <= '0';
    EN <= '1';
    SDI <= '0';
    STRB <= '0';
    SYNC <= '0';
    wait for 5*Period;
    RST <= '1';
    
    --Begin Test1
    F40 := "1101001111010011110100111101001111011111"; --Random sequence 40 bits long with trailing ones to test zeroPadding.
    SYNC <= '1';
    wait for 4*Period;
    SYNC <= '0';
    STRB <= '1'; --Force to one assuming memory controller reads in time. *************
    for loopVar in 39 downto 0 loop
      SDI <= F40(loopVar);
      wait for Period;
    end loop;
    wait for 6*Period; --JTAG crap bits that will never be recorded
    Dat384 := x"CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC"; --24 words, 96 nibbles="1100"
    for loopVar in 383 downto 0 loop
      SDI <= Dat384(loopVar);
      wait for Period;
    end loop;
    --End Test1
    
    
    wait for 10*Period;
    --Begin Test2
    F40 := "1101001111010011110100111101001111011111"; --Random sequence 40 bits long with trailing ones to test zeroPadding.
    SYNC <= '1';
    wait for 4*Period;
    SYNC <= '0';
    STRB <= '1'; --Force to one assuming memory controller reads in time. *************
    for loopVar in 39 downto 0 loop
      SDI <= F40(loopVar);
      wait for Period;
    end loop;
    wait for 6*Period; --JTAG crap bits that will never be recorded
    Dat384 := x"CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC"; --24 words, 96 nibbles="1100"
    for loopVar in 383 downto 40 loop
      SDI <= Dat384(loopVar);
      wait for Period;
    end loop;
    EN <= '0';
    wait for 10*Period;
    EN <= '1';
    --End Test2
    
      
    

    wait;
  end process;
end TEST;